How to Learn Scanning Capacitance Microscopy (SCM): From Local MOS Capacitance and dC/dV to Dopant Profiles, Junctions and Semiconductor Device Metrology

## Wait, What? SCM Does Not Measure Dopant Atoms Directly A semiconductor can contain one chemical dopant concentration but a different electrically active carrier concentration. SCM does not count arsenic, boron, phosphorus or aluminium atoms. Instead, the conductive tip, surface dielectric and semiconductor form a tiny MOS capacitor. Apply a small AC voltage. The semiconductor depletion region expands and contracts. The capacitance changes. That differential capacitance becomes the image. > **SCM maps the local electrical response of a nanoscale MOS structure. Dopant concentration is an inference built on semiconductor electrostatics, oxide quality, carrier mobility, tip geometry and calibration.** ## The One-Sentence Answer **Learn SCM by tracing conductive tip → local MOS capacitor → high-frequency capacitance → AC bias modulation → \(dC/dV\) → carrier-type and concentration contrast, then add oxide thickness, interface traps, mobility, tip wear, cross-section preparation and finite-element calibration before turning image intensity into a quantitative dopant profile.** # Beginner Layer — Build the Tiny MOS Capacitor ## Stage 1: A Conductive Tip Replaces the Metal Gate A metal-coated AFM probe contacts or closely approaches a thin insulating layer on a semiconductor. The stack is conceptually: **metal tip → oxide/dielectric → semiconductor** ## Stage 2: The Semiconductor Charge Distribution Depends on Bias A local gate voltage can create: – accumulation; – depletion; – inversion. ## Stage 3: The Capacitance Therefore Depends on Voltage A conventional MOS C–V curve already contains doping and interface information. SCM miniaturizes that experiment. # Why SCM Uses Two Frequencies ## Stage 4: A High-Frequency Capacitance Sensor Measures Tip–Sample Capacitance Classic SCM instruments use a radio-frequency or microwave resonant circuit around the tip–sample capacitor. NIST describes a 1-GHz-class tuned circuit in the established SCM architecture. ## Stage 5: A Much Lower-Frequency AC Voltage Modulates the Semiconductor A kHz-scale AC bias moves the local depletion width. ## Stage 6: A Lock-In Amplifier Detects the Differential Response The resulting signal is approximately proportional to: **dC/dV** rather than raw capacitance alone. This two-frequency architecture is one of the most important ideas in SCM. # Carrier-Type Contrast ## Stage 7: p-Type and n-Type Regions Respond With Opposite Polarity Under the instrument’s bias convention, the sign of the differential capacitance can reverse across a p–n junction. ## Stage 8: The Sign Is Instrument-Convention Dependent The image colour should never be interpreted without knowing: – tip bias convention; – lock-in reference phase; – amplifier sign. ## Stage 9: A Bright/Dark Boundary Is Not Automatically the Metallurgical Junction The apparent electrical transition can move with DC bias. # Carrier-Concentration Layer ## Stage 10: Differential Capacitance Depends on Depletion Width Higher carrier concentration generally produces a thinner depletion region. ## Stage 11: SCM Contrast Is Therefore Related to Carrier Concentration In simplified regimes, \(dC/dV\) varies strongly with the local doping level. ## Stage 12: The Relationship Is Not Universally Linear Absolute concentration requires a calibration curve or semiconductor electrostatic model. > **SCM image intensity is an electrical transfer function, not a periodic table.** # Local C–V Spectroscopy ## Stage 13: Stop the Scan and Sweep DC Bias at One Position This produces a local capacitance-response curve. ## Stage 14: Local C–V Helps Separate Carrier Type From Instrument Gain Two points with similar image intensity can have very different voltage dependence. ## Stage 15: Local Spectroscopy Is Stronger Than One-Colour Imaging A quantitative claim should survive both: – spatial mapping; – bias-dependent spectroscopy. # Oxide / Dielectric Layer ## Stage 16: The Surface Dielectric Is Part of the MOS Capacitor Its thickness and permittivity strongly affect the measured capacitance. ## Stage 17: Oxide Nonuniformity Can Look Like Doping Contrast A thinner oxide can increase capacitance without changing the semiconductor. ## Stage 18: Cross-Sectional Silicon Often Requires Controlled Oxidation Classic NIST work developed low-temperature oxide preparation specifically because harsh thermal oxidation would alter the device being measured. ## Stage 19: High-k Dielectrics Create Their Own SCM Physics SCM can characterize local dielectric quality, but the same signal is now influenced by: – dielectric constant; – trapped charge; – interface state density. # Interface Traps and Surface Mobility ## Stage 20: Interface States Exchange Charge With the Semiconductor Their ability to follow the modulation frequency changes the C–V response. ## Stage 21: Surface Mobility Can Degrade Near Defects or Damaged Cross Sections At RF sensing frequencies, series resistance can distort the apparent capacitance. ## Stage 22: NIST Modelling Shows This Can Bias Dopant Extraction A quantitative profile must treat surface preparation as part of the electrical device. # Cross-Sectional SCM ## Stage 23: Cleave or Polish Across a Semiconductor Device The scan can traverse: – source; – channel; – drain; – wells; – junctions. ## Stage 24: The Cross Section Creates a New Surface Polishing, FIB preparation or oxidation can modify: – damage; – traps; – mobility; – surface charge. ## Stage 25: The Measured Cross Section Is Not the Buried Device Before Preparation Professional SCM keeps the preparation history visible. # Junction Position ## Stage 26: Bias Can Shift the Apparent Electrical Boundary A junction image reflects depletion electrostatics, not merely the location where dopant atoms cross. ## Stage 27: Finite-Element Poisson Modelling Can Recover the Metallurgical Junction More Reliably NIST work demonstrated measured/modelled SCM agreement across p–n structures and showed why operating point matters. # Spatial Resolution ## Stage 28: Tip Radius Is Important—but Not Alone Resolution also depends on: – depletion width; – dielectric thickness; – stray capacitance; – contact geometry. ## Stage 29: A 10-nm Tip Does Not Guarantee a 10-nm Dopant Profile The electrical field samples a finite volume. ## Stage 30: The Junction Itself Has Physical Width Electrical transition width can reflect real depletion plus measurement broadening. # Stray Capacitance ## Stage 31: The Tip Cone and Cantilever Add Capacitance The useful nanoscale signal may be a tiny fraction of the total. ## Stage 32: Instrument Electronics Reject Much of the Background But residual stray capacitance still influences quantitative sensitivity. ## Stage 33: Edge Geometry Can Reduce Stray Contributions in Specialized Experiments Recent perovskite SCM work explicitly optimized geometry to improve contrast. # Tip Wear and Contact Force ## Stage 34: SCM Often Operates in Contact Tip pressure can change: – contact area; – oxide condition; – local surface state. ## Stage 35: Tip Wear Changes Electrical and Spatial Transfer Functions Recalibration is necessary during long quantitative studies. # Wide-Bandgap and Compound Semiconductors ## Stage 36: SCM Is Not Limited to Silicon It has been applied to: – III–V devices; – SiC; – GaN; – high-k dielectric stacks. ## Stage 37: Wide-Bandgap Materials Can Have Stronger Interface-State Problems Native oxides and surface preparation can dominate. # 2025 Perovskite Frontier ## Stage 38: SCM Has Recently Been Extended to Halide Perovskites A 2025 *Journal of Physical Chemistry C* study used an ALD-grown Al₂O₃ layer to form a controlled insulating interface and mapped carrier concentration/type in perovskite films. ## Stage 39: The Experiment Demonstrates Why the Dielectric Must Be Engineered The authors optimized: – oxide thickness; – tip choice; – stray-capacitance geometry; – illumination conditions. ## Stage 40: Perovskite SCM Is Therefore a Measurement-System Problem A carrier map is inseparable from interface fabrication and ionic/electronic history. # Illumination and Nonequilibrium SCM ## Stage 41: Light Changes Carrier Populations Illuminated SCM can probe photoinduced carrier redistribution. ## Stage 42: Slow Ionic Motion Can Complicate Perovskites A local C–V response can contain both electronic and ionic contributions. The perovskite canonical owns the material mechanism; SCM owns the local capacitance receiver. # SCM Versus Neighboring Methods ## Stage 43: SCM Versus KPFM KPFM measures contact-potential-related electrostatics. SCM measures local voltage-dependent capacitance. ## Stage 44: SCM Versus MIM MIM measures complex microwave admittance. SCM deliberately modulates a MOS depletion region and detects \(dC/dV\). ## Stage 45: SCM Versus Conductive AFM C-AFM measures direct current. SCM can map electrically insulating MOS stacks with no DC current path through the oxide. # Machine-Assisted Quantitation ## Stage 46: Finite-Element Modelling Is Already Central to SCM Poisson-equation solutions translate local geometry and doping into expected C–V response. ## Stage 47: ML Can Accelerate the Inverse Problem A model can map topography + \(dC/dV\) + bias to carrier concentration. ## Stage 48: Training Must Include Oxide and Tip Variation Otherwise the network may mistake interface geometry for doping. # Professional Layer ## Stage 49: Separate Five Objects 1. true electrically active carrier/dopant distribution; 2. local MOS electrostatics; 3. dielectric/interface response; 4. RF capacitance + lock-in measurement; 5. inferred carrier profile. ## Stage 50: Professional SCM Is a MOS–Interface–Calibration Inverse Problem > **Which carrier concentration or junction profile remains identifiable after oxide thickness, interface traps, surface mobility, tip geometry, contact force, stray capacitance and preparation damage are all allowed to explain the same \(dC/dV\) map?** # Evidence: What Makes an SCM Claim Strong? Stronger evidence combines simultaneous topography, local \(dC/dV\)–bias curves, known doping standards, oxide thickness measurement, repeat tips, contact-force series, cross-sectional preparation controls, finite-element modelling, SIMS/SSRM/KPFM/MIM comparison and carrier-type sign validation. # Misconceptions Worth Hunting – SCM directly counts dopant atoms. – \(dC/dV\) is the same as capacitance. – Bright contrast always means high doping. – p and n regions always have universal colours. – Tip radius alone sets SCM resolution. – Oxide thickness does not matter. – Interface traps only affect MOS reliability, not SCM. – The apparent junction boundary always equals the metallurgical junction. – A cross section reveals the untouched buried device. – Quantitative carrier concentration can be read directly from an uncalibrated image. – MIM, KPFM and SCM all measure the same electrical property. # Transfer Check A nominally uniform-doping region shows strong SCM contrast exactly where oxide thickness changes. Did carrier concentration necessarily change? **No. The MOS dielectric changed.** A junction boundary moves when DC bias changes. Did the dopant atoms move? **No. Depletion electrostatics changed.** A 2025 perovskite SCM map changes under illumination. Does that automatically mean permanent doping changed? **No. Photo-carriers and ionic/electronic redistribution are alternatives.** A tip gives progressively weaker contrast during a long scan. Did the device become more uniform? **Not necessarily. Tip wear is a strong alternative.** # How We Know the Learning Has Held A learner should be able to explain the local MOS capacitor, distinguish raw capacitance from \(dC/dV\), explain RF sensing plus low-frequency modulation, interpret p/n contrast, explain why concentration needs calibration, explain local C–V spectroscopy, identify oxide/interface and mobility effects, explain junction-position bias, explain cross-section preparation artifacts, compare SCM with KPFM, MIM and C-AFM, explain recent perovskite SCM and identify quantitative inversion limits. # Model Limits SCM is strongest for samples that can form a stable tip–dielectric–semiconductor structure. It does not directly output chemical dopant concentration, carrier mobility, trap density or absolute junction position without additional models or measurements. Professional SCM keeps **tip state + dielectric thickness + carrier type + DC bias + AC modulation + RF capacitance + contact force + surface mobility + interface traps + calibration + orthogonal device evidence** visible together. # Teaching Guide Teach in this order: **MOS capacitor → accumulation/depletion/inversion → capacitance → RF sensing → AC modulation → \(dC/dV\) → carrier type → concentration → local C–V → oxide/interface → mobility → cross-section → junction modelling → compound semiconductors → perovskites → quantitative inversion → validation.** # Connect This to the eduKate Learning Estate – Atomic Force Microscopy — topography and probe mechanics. – Kelvin Probe Force Microscopy — contact potential and band bending. – Microwave Impedance Microscopy — local GHz complex admittance. – Deep-Level Transient Spectroscopy — deep defect kinetics. – Semiconductors and Transistors — device mechanism owner. # Research Foundations and Further Learning – NIST, *Scanning Capacitance Microscopy for Electrical Characterization of Semiconductors and Dielectrics*. – NIST, *Semiconductor Dopant Profiling and Dielectric Characterization with Scanning Capacitance Microscopy*. – NIST, modelling of SCM images across p–n junctions. – NIST, interface traps and surface-mobility effects in SCM. – IBM / Applied Physics Letters foundational lateral dopant profiling work. – *Direct Measurement of Carrier Distribution in Perovskite by Scanning Capacitance Microscopy*, *Journal of Physical Chemistry C*, 2025. # The Quiet Ending The beginner asks, “Which side of the junction is p-type?” The developing semiconductor scientist asks, “How did the local depletion capacitance create that contrast?” The advanced learner asks, “How much of the image belongs to carrier concentration, and how much to oxide, interface traps or tip geometry?” And the professional asks: > **Which electrically active carrier profile survives after the nanoscale MOS capacitor itself is treated as part of the measurement?**